Comparators are used in a variety of applications. For example, comparators may be used for comparison of two numbers or operands in processing systems. For example, memory structures like caches may use comparators for comparing a desired address (or portion thereof) to be searched, with addresses (or portions thereof) stored in the caches (also known as “tags”) to determine whether the desired address is present (cache hit) or not present in the cache (cache miss). Some arithmetic and logic units (ALUs) of processors may use comparators for comparison operations such as greater-than, less-than, equal-to, etc. In some cases, comparators may also be used to test conditions (e.g., for conditional instructions), set predicate registers (for predicated instructions), etc.
Comparators may be implemented using hardware, for example, with specially designed circuits for improving the speed of comparison of two multi-bit numbers. In this regard, wide (e.g., multi-bit) comparators are conventionally implemented using domino complementary metal-oxide semiconductor (CMOS), pseudo-static CMOS, skewed CMOS, or similar technologies as known in the art. In these conventional implementations, the comparators receive the numbers to be compared in a differential form (i.e., true and complement versions of the numbers are be provided as inputs). Conventionally, the comparators are designed as domino logic (e.g., cascaded structures with multiple stages). Correct functionality of domino logic based comparators is achieved when the differential inputs are free of glitches. Achieving glitch-free inputs is difficult.
Considering the above example application of comparators in cache structures, the stored addresses or tags in the cache are single-ended domino signals. As used herein, single-ended signals refer to signals which are not differential. However, in order to be used as an input to a comparator for comparing the tags with a desired address to be searched, the single-ended domino inputs in their native form need to be converted to differential domino inputs. Conversion to differential domino input may entail providing the native single-ended input as a “true” part and generating an inverted version of the single-ended input for a “complement” part. To generate the complement part, the true part may be inverted and combined with a timed clock in order to generate a glitch-free domino signal. While the generation of the complement part may use expensive logic (in terms of area and power), there is also potential for race conditions to develop between the clock used by the comparator and the timed clock used to generate the complement part. Increasing process variations can lead to exacerbating the race conditions, in turn calling for higher timing margins, to meet timing constraints for the comparator circuits under varying process-voltage-temperature (PVT) corners or PVT conditions.
Accordingly, there is a need in the art to avoid the drawbacks of differential domino inputs in conventional implementations of comparators.